Method and system for creating and verifying structural logic model of electronic design from behavioral description, including generation of logic and timing models
US5933356A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 5, 1996 |
| Grant date | Aug 3, 1999 |
| Priority date | — |
| Expiry date | Nov 5, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3308
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A system and method are provided herein for creating and validating an electronic design structural description of a circuit or device from a VHDL description of the circuit or device which includes a compiler for compiling the VHDL description of the circuit or device; a device for locating problems within the compiled description and measuring the effectiveness of solving the problems; a device for passing information including the compiled description to a physical design level; a physical design tool for receiving the information and creating a physical design therefrom; and a device for back annotating the information from the physical design tool to the compiler.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.