Method and circuit for testing a semiconductor memory device operating at high frequency
US5933379A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 1998 |
| Grant date | Aug 3, 1999 |
| Priority date | — |
| Expiry date | Mar 30, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit for testing a semiconductor memory device comprises a latency controller for controlling the latency of the external clock signal, an internal column address generator for generating a column address signal in the memory device, and a mode register for generating a mode signal. The circuit for testing semiconductor memory devices also includes a column address decoder for decoding the output address signal of the internal column address generator, a memory cell for reading or writing data, an input/output control unit for controlling the data input/output of the memory cell according to the output signal of the latency controller, a data input buffer, and a data output buffer. Further provided are a frequency multiplier for generating an internal clock signal having a frequency "n" times the frequency of the external clock signal. By providing the above-mentioned improvements, the conventional test equipment can be used to test high frequency memory devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.