Attachment method for stacked integrated circuit (IC) chips
US5933712A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 19, 1998 |
| Grant date | Aug 3, 1999 |
| Priority date | — |
| Expiry date | Mar 19, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06579
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An attachment method for stacked integrated circuit (IC) chips. The method involves connecting stacked chips, such as DRAM memory chips, to each other and/or to a circuit board. Pads on the individual chips are rerouted to form pads on the side of the chip, after which the chips are stacked on top of each other whereby desired interconnections to other chips or a circuit board can be accomplished via the side-located pads. The pads on the side of a chip are connected to metal lines on a flexible plastic tape (flex) by anisotropically conductive adhesive (ACA). Metal lines on the flex are likewise connected to other pads on chips and/or to pads on a circuit board. In the case of a stack of DRAM chips, pads to corresponding address lines on the various chips may be connected to the same metal line on the flex to form an address bus. This method has the advantage of reducing the number of connections required to be made to the circuit board due to bussing; the flex can accommodate dimensional variation in the alignment of chips in the stack; bonding of the ACA is accomplished at low temperature and is otherwise simpler and less expensive than solder bonding; chips can be bonded to the…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.