Method of controlling etch bias with a fixed lithography pattern for sub-micron critical dimension shallow trench applications

US5933759A · kind A · utility

Assignee

• Intel Corporation · US

Inventors

• Phi L. Nguyen · Hillsboro, US
• Ralph A. Schweinfurth · Portland, US
• Swaminathan Sivakumar · Portland, US

Key dates

• Filing date: Dec 31, 1996
• Grant date: Aug 3, 1999
• Expiry date: Dec 31, 2016

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/3065
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

The present invention describes a method for forming submicron critical dimension shallow trenches with improved etch selectivity and etch bias control. In one embodiment of the present invention, three separate etch steps are performed. A polish stop layer (or an etch hard mask layer) and an oxide layer are etched during the first and second etch steps and the underlying substrate is etched during the third etch step. In the first etch step a carbon-fluorine based etchant is used in order to form a polymer layer along the photoresist, polish stop layer (or etch hard mask layer), and oxide layer. After the first etch step, a second etch step is used to remove the polymer from the horizontal surfaces of the semiconductor structures thereby forming polymer sidewalls as well as completing the etching of the polish stop layer (or etch hard mask layer) and the oxide layer. Polymer sidewalls protect the photoresist, polish stop layer (or etch hard mask layer), and oxide layer during the third etch step thereby improving the etch selectivity and etch bias control. The third etch step completes the formation of the trench by etching the substrate.