Phi L. Nguyen
7Patents
7h-index
10Co-inventors
52Inventor score
Filing activity: Jan 23, 1996 → Oct 8, 2003
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5843846A | Etch process to produce rounded top corners for sub-micron silicon trench applications | Electricity | 49 | Expired |
| US6958547B2 | Interconnect structures containing conductive electrolessly deposited etch stop layers, liner layers, and via plugs | Electricity | 42 | Expired |
| US7008872B2 | Use of conductive electrolessly deposited etch stop layers, liner layers and via plugs in interconnect structures | Electricity | 30 | Expired |
| US6968532B2 | Multiple exposure technique to pattern tight contact geometries | Physics | 27 | Expired |
| US5933759A | Method of controlling etch bias with a fixed lithography pattern for sub-micron critical dimension shallow trench applications | Electricity | 26 | Expired |
| US6472315B2 | Method of via patterning utilizing hard mask and stripping patterning material at low temperature | Electricity | 13 | Expired |
| US6001699A | Highly selective etch process for submicron contacts | Electricity | 12 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.