Accelerated graphics port memory mapped status and control registers
US5936640A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 1997 |
| Grant date | Aug 10, 1999 |
| Priority date | — |
| Expiry date | Sep 30, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1081
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. A plurality of AGP memory-mapped status and control registers are stored in the computer system memory, and are used for status and control of AGP functions in the computer system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.