Bi-layer programmable resistor memory
US5936880A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 13, 1997 |
| Grant date | Aug 10, 1999 |
| Priority date | — |
| Expiry date | Nov 13, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A static, in-circuit programmable memory device is provided where the storage element employed is a bi-layer programmable resistor. A specialized programming and readout circuit is provided for each storage element, allowing a known word-line/bit-line memory architecture (commonly used with fuse type memories) to be adapted to a memory element that conducts in both of two different states. The programming and readout circuit may take the form of a merged bipolar/FET device. A bipolar transistor is used for programming and also provides a diode action to prevent sneak path currents from flowing when a storage element is not selected. The bipolar transistor may be a parasitic bipolar transistor. An FET is used for readout. Storage elements are paired, one storage element of each pair functioning as a reference element. The bit lines of the paired storage elements are connected to a current mirror circuit that effects a comparison between current through the reference element and current through its paired storage element. Reliable readout is thereby attained.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.