Method for forming a line-on-line multi-level metal interconnect structure for use in integrated circuits
US5937324A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 13, 1998 |
| Grant date | Aug 10, 1999 |
| Priority date | — |
| Expiry date | Mar 13, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor component with a multi-level interconnect system includes providing a substrate (11), fabricating a device (12) in the substrate (11), forming an interconnect layer (15) over the substrate (11), depositing a dielectric layer (20) over the interconnect layer (15), depositing a separate interconnect layer (21) over the dielectric layer (20), etching a via (31) in the separate interconnect layer (21) and in the dielectric layer (20), and depositing a different interconnect layer (40) over the separate interconnect layer (21) and in the via (31) wherein the another interconnect layer (40) electrically couples the interconnect layer (15) and the separate interconnect layer (21).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.