Network interface circuit including an address translation unit and flush control circuit and method for checking for invalid address translations
US5937436A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 1, 1996 |
| Grant date | Aug 10, 1999 |
| Priority date | — |
| Expiry date | Jul 1, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1027
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A network interface circuit including an address translation unit and a flush check circuit, and a method for checking for an invalid address translation within of the address translation unit, are disclosed. A flush check circuit, in communication with the address translation unit, is implemented to determine, prior to loading an address translation into the internal memory, whether one of the plurality of entries already contains a virtual address utilized by the address translation. If so, an error has occurred with the flushing operations of the address translation unit because the address translation should have already been removed. In response, the flush check circuit signals logic to perform error handling techniques such as issuing an error signal, storing the invalid address translation unit, or transmitting the virtual address of the address translation without loading that address translation. The memory of the address translation unit may include a content addressable memory (CAM) element configured to contain the virtual page number of an address translation, and a random access memory (RAM) element configured to contain a physical page number of that address translat…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.