Apparatus and method for selectively controlling clocking and resetting of a network interface
US5938728A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 1997 |
| Grant date | Aug 17, 1999 |
| Priority date | — |
| Expiry date | Oct 30, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A network interface for a workstation, configured to be powered down to a standby mode while the network interface remains in a powered-up condition, includes a bypass circuit configured to enable configuration registers in the network interface to complete loading of configuration information in a known state, regardless of an absence of an external data clock from the network during the initialization interval. The bypass circuit ensures that the configuration registers in the network interface that require a network clock (e.g., a transmit clock or a receive clock) are maintained in a known state to enable the network interface to be independently initialized. One example of the bypass circuit holds a power on reset signal until the necessary network clock signal is detected for a predetermined number of detected clock cycles. Another example of the bypass circuit substitutes the absent clock signal with an independent clock source in response to the power on reset signal and holds the power on reset signal for a predetermined number of independent clock cycles, followed by switching back to the signal path providing the required clock signal. The disclosed arrangement enables t…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.