Semiconductor memory device and manufacturing method of the same
US5939746A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 12, 1996 |
| Grant date | Aug 17, 1999 |
| Priority date | — |
| Expiry date | Dec 12, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/033
Abstract
A storage node electrode is connected to a contact plug via an upper node contact hole. A lower cell plate electrode composed of an N type silicon film and an N type silicon film spacer is covered by the storage node electrode via a titanium oxide film as a lower capacitive insulating film and an upper cell plate electrode composed of an N type silicon film connected to the lower cell plate electrode covers the storage node electrode via a titanium oxide film as an upper capacitive insulating film. Thus, in a DRAM having a stacked and COB type memory, a surface ratio of the storage node electrode, contributing to a capacitor, is increased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.