Method and apparatus for testing quiescent current in integrated circuits
US5939897A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 11, 1998 |
| Grant date | Aug 17, 1999 |
| Priority date | — |
| Expiry date | Feb 11, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3004
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method and apparatus for obtaining near 100 percent quiescent current test coverage within a reasonable amount of time is accomplished by providing a plurality of test circuits interdisposed between a plurality of combinational logic circuits. During testing, the testing circuits isolate the input of one combinational logic circuit from the output of the preceding combinational logic, thus allowing the test circuit to stimulate the input of the combinational logic circuit. By performing the input stimulations of the plurality of combinational logic circuits simultaneously, only two test steps are needed to check the quiescent current of the plurality of combinational logic circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.