Switchable N-well biasing technique for improved dynamic range and speed performance of analog data bus
US5939936A · kind A · utility
7Cited by
9References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 6, 1998 |
| Grant date | Aug 17, 1999 |
| Priority date | — |
| Expiry date | Jan 6, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0018
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit that includes at least two driver circuits. Each driver circuit receives analog information and drives a value related to the analog information to an analog bus. Each driver circuit also includes a select transistor to pass the value related to the analog information to the analog bus when the driver circuit is selected. The select transistor includes a source and a bulk. Each driver circuit further includes a bulk potential control circuit (BPCC) to couple the bulk to the source when the driver circuit is selected and to couple the bulk to a voltage supply when the driver circuit is not selected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.