Semiconductor ESD protection circuit
US5940258A · kind A · utility
43Cited by
3References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 5, 1997 |
| Grant date | Aug 17, 1999 |
| Priority date | — |
| Expiry date | Feb 5, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/811
Abstract
Protection circuitry (10) for protecting an integrated circuit from an ESD pulse is provided. The protection circuitry (10) includes discharge circuitry (14) on a substrate (11) that discharges an ESD pulse to the integrated circuit to ground (18). The protection circuitry (10) also includes a substrate bias generator (25) that uses a portion of the ESD pulse's energy to bias the substrate (11) of the discharge circuitry (14).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.