Method and apparatus for emulating multi-ported memory circuits
US5940603A · kind A · utility
56Cited by
34References
26Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 17, 1997 |
| Grant date | Aug 17, 1999 |
| Priority date | — |
| Expiry date | Oct 17, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory design is implemented in static memory circuits having a plurality of bidirectional access ports, wherein each port is configured for read or write access. The memory design defines initial contents, depth, width, and bank selection in the memory circuits according to predefined configuration values, as well as, for each access port, whether that access port is configured for read or write. Port access occurs during time slots, which are based on external clock signals and memory circuit access times. Modified memory designs may be implemented such that access ports are accordingly reconfigured.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.