Field effect transistor process with semiconductor mask, single layer integrated metal, and dual etch stops
US5940694A · kind A · utility
Inventors
Key dates
| Filing date | Jul 22, 1996 |
| Grant date | Aug 17, 1999 |
| Priority date | — |
| Expiry date | Jul 22, 2016 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/951
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a periodic table group III-IV field-effect transistor device is described. The disclosed fabrication arrangement uses a single metallization for ohmic and Schottky barrier contacts, employs selective etching with a permanent etch stop layer, employs a non-alloyed ohmic contact semiconductor layer and includes a permanent semiconductor material secondary mask element, a mask element which can be grown epitaxially during wafer fabrication. The invention includes provisions for both an all optical lithographic process and a combined optical and electron beam lithographic process These concepts are combined to provide a field-effect transistor device of reduced fabrication cost, increased dimensional accuracy and state of the art electrical performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.