Cache address generation with and without carry-in
US5940877A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 12, 1997 |
| Grant date | Aug 17, 1999 |
| Priority date | — |
| Expiry date | Jun 12, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6082
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache system provides for accessing set associative caches with no increase in critical path delay, for reducing the latency penalty for cache accesses, for reducing snoop busy time, and for responding to MRU misses and cache misses. The cache array is accessed by multiplexing two most-recently-used (MRU) arrays which are addressed and accessed substantially in parallel with effective address generation, the outputs of which MRU arrays are generated, one by assuming a carryin of zero, and the other by assuming a carryin of one to the least significant bit of the portion of the effective addressed used to access the MRU arrays. The hit rate in the MRU array is improved by hashing within an adder the adder's input operands with predetermined additional operand bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.