Tunable threshold SOI device using back gate well
US5942781A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Jun 8, 1998 |
| Grant date | Aug 24, 1999 |
| Priority date | — |
| Expiry date | Jun 8, 2018 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/901
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A fully depleted SOI device includes a semiconductor substrate and a conductive well of a first conductivity type formed in a principal surface of the semiconductor substrate. An insulating layer is formed along the principal surface of the semiconductor substrate and extends across the conductive well. A transistor is formed on the insulating layer such that the insulating layer is interposed between the transistor and the semiconductor substrate, with the transistor including source and drain regions of the first conductivity type formed on the insulating layer, a channel region of a second conductivity type formed on the insulating layer and aligned over the conductive well, and a gate electrode aligned over the channel region. A metal contact is connected to the conductive well for applying a reverse bias potential to the transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.