PLD with split multiplexed inputs from global conductors
US5942914A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 19, 1997 |
| Grant date | Aug 24, 1999 |
| Priority date | — |
| Expiry date | Jun 19, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1778
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An improved multiplexer arrangement for connecting global conductors to logic array block (LAB) inputs. A single connection connects a particular global conductor to an input path to LABs on both sides of the interconnect region in a folded LAB architecture. The number of connections to the global conductors is thus reduced, reducing the number of transistors needed to make those connections and the corresponding loading of the global conductors. The connections to two paths are part of a first level multiplexer. A second-level multiplexer connected to each LAB line is also provided to add back some of the flexibility lost by having each global conductor connection connect to two paths. The invention cuts the number of transistors needed to connect to the global conductors in half, while adding some transistors for the second-level multiplexers, with a net reduction in connection transistors of about 1/3.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.