Semiconductor memory device with efficient layout
US5943253A · kind A · utility
9Cited by
4References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 9, 1998 |
| Grant date | Aug 24, 1999 |
| Priority date | — |
| Expiry date | Apr 9, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/063
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes at least one cell block including an array of memory cells, a plurality of sense amplifiers which temporarily hold data of the memory cells, a first data bus connected to the plurality of sense amplifiers via first gates, and a second data bus having a direct electrical connection to the first data bus and being laid out to extend through a position of the at least one cell block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.