Read only memory
US5943255A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 27, 1998 |
| Grant date | Aug 24, 1999 |
| Priority date | — |
| Expiry date | Mar 27, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B20/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The read only memory has a plurality of conductor track planes one above the other. The conductor tracks in adjacent planes are oriented such that they intersect in intersecting regions. In these intersecting regions, either a VIA tunnel contact is provided, which represents a logic "1" or no VIA tunnel contact is provided, so that this intersecting region represents a logic "0". In this way, over the same surface area, a plurality of memory cells can be produced one above the other. The read only memory is produced with a defined sequence of process steps and it is operated by selectively applying predetermined voltages across the various conductor tracks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.