Apparatus and method for minimizing address hold time in asynchronous SRAM
US5943288A · kind A · utility
10Cited by
5References
5Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 31, 1997 |
| Grant date | Aug 24, 1999 |
| Priority date | — |
| Expiry date | Oct 31, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A write control circuit and method for an asynchronous SRAM that minimizes the write address hold time required to prevent data from being written to incorrect addresses in the memory. The write control circuit temporarily disables a write circuit in the memory whenever the memory address changes. The delay of the write control circuit from input to output is shorter than the delay of a decoder in the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.