Distributed logic analyzer for use in a hardware logic emulation system
US5943490A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 30, 1997 |
| Grant date | Aug 24, 1999 |
| Priority date | — |
| Expiry date | May 30, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3185
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A hardware emulation system is disclosed which reduces hardware cost by time-multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The reconfigurable logic system of the present invention comprises a plurality of reprogrammable logic devices, and a plurality of reprogrammable interconnect devices. The logic devices and interconnect devices are interconnected together such that multiple design signals share common I/O pins and circuit board traces. A logic analyzer for a hardware emulation system is also disclosed. The logic circuits necessary for executing logic analyzer functions is programmed into the programmable resources in the logic chips of the emulation system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.