BiCMOS process for forming double-poly MOS and bipolar transistors with substantially identical device architectures

US5943564A · kind A · utility

Assignee

• NATIONAL SEMICONDUCTOR CORPORATION · US

Inventors

• Hung-Sheng Chen · San Jose, US
• Chih Sieh Teng · San Jose, US

Key dates

• Filing date: Feb 13, 1996
• Grant date: Aug 24, 1999
• Expiry date: Feb 13, 2016

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0109

Abstract

A fully complementary double-poly BiCMOS process utilizes substantially identical device architectures to form n-channel and p-channel MOS transistors, as well as npn and pnp bipolar transistors. In the double-poly process, the first layer of polysilicon is utilized to form the source and drain of the MOS transistors as well as the base and collector of the bipolar transistors. The second layer of polysilicon is then utilized to form the gate of the MOS transistors as well as the emitter of the bipolar transistors.