Hung-Sheng Chen
55Patents
12h-index
39Co-inventors
84Inventor score
Filing activity: Oct 7, 1994 → Aug 21, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6004862A | Core array and periphery isolation technique | Electricity | 181 | Expired |
| US5602404A | Low voltage triggering silicon controlled rectifier structures for ESD protection | Electricity | 61 | Expired |
| US5907781A | Process for fabricating an integrated circuit with a self-aligned contact | Electricity | 41 | Expired |
| US7245535B2 | Non-volatile programmable memory cell for programmable logic array | Physics | 31 | Expired |
| US9048569B2 | Wire-to-board connector assembly and board-end connector thereof | Electricity | 28 | Active |
| US6660585B1 | Stacked gate flash memory cell with reduced disturb conditions | Physics | 26 | Expired |
| US5943564A | BiCMOS process for forming double-poly MOS and bipolar transistors with substantially identical device architectures | Electricity | 25 | Expired |
| US5605849A | Use of oblique implantation in forming base of bipolar transistor | Emerging Cross-Sectional Technologies | 16 | Expired |
| US5733813A | Method for forming planarized field isolation regions | Electricity | 15 | Expired |
| US6841846B1 | Antifuse structure and a method of forming an antifuse structure | Electricity | 15 | Expired |
| US6124640A | Scalable and reliable integrated circuit inter-level dielectric | Electricity | 14 | Expired |
| US6258668A | Array architecture and process flow of nonvolatile memory devices for mass storage applications | Physics | 14 | Expired |
| US5726069A | Use of oblique implantation in forming emitter of bipolar transistor | Electricity | 12 | Expired |
| US6134150A | Erase condition for flash memory | Physics | 12 | Expired |
| US5945352A | Method for fabrication of shallow isolation trenches with sloped wall profiles | Emerging Cross-Sectional Technologies | 12 | Expired |
| US5607873A | Method for forming contact openings in a multi-layer structure that reduces overetching of the top conductive structure | Electricity | 11 | Expired |
| US6717846B1 | Non-volatile semiconductor memory having split-gate memory cells mirrored in a virtual ground configuration | Physics | 10 | Expired |
| US6232646A | Shallow trench isolation filled with thermal oxide | Electricity | 7 | Expired |
| US6444539B1 | Method for producing a shallow trench isolation filled with thermal oxide | Electricity | 6 | Expired |
| US7590000B2 | Non-volatile programmable memory cell for programmable logic array | Physics | 6 | Active |
| US9304548B2 | Docking station of electronic device | Electricity | 5 | Active |
| US6808988B1 | Method for forming isolation in flash memory wafer | Electricity | 4 | Expired |
| US5899723A | Oblique implantation in forming base of bipolar transistor | Emerging Cross-Sectional Technologies | 3 | Expired |
| US10141252B2 | Semiconductor packages | Electricity | 3 | Active |
| US6103593A | Method and system for providing a contact on a semiconductor device | Emerging Cross-Sectional Technologies | 3 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.