Method of shared intervention via a single data provider among shared caches for SMP bus
US5943685A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 14, 1997 |
| Grant date | Aug 24, 1999 |
| Priority date | — |
| Expiry date | Apr 14, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0831
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of improving memory latency associated with a read-type operation in a multiprocessor computer system is disclosed. A requesting processing unit issues a message to an interconnect of the computer system indicating that the requesting processing unit desires to read a value from an address of a memory device of the computer system, and each cache snoops the interconnect to detect the message. Each cache thereafter transmits a response to the message, the response selected from the group consisting of an invalid response, a modified intervention response, a shared intervention response, or an alternative response, wherein the invalid response indicates that a cache does not contain any value corresponding to the address of the memory device, the modified intervention response indicates that a cache contains and can source a modified value corresponding to the address of the memory device, and the shared intervention response indicates that a cache contains and can source an unmodified value corresponding to the address of the memory device. A priority can be associated with each response from each cache, and the responses detected by system logic, the system logic forwardin…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.