Combined adder and logic unit

US5944772A · kind A · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Juergen Haas · Knittlingen, DE
• Wilhelm Haller · Winnenden, DE
• Ulrich Krauch · Waldenbuch, DE
• Thomas Ludwig · Sindelfingen, DE
• Holger Wetter · Holzgerlingen, DE

Key dates

• Filing date: Nov 13, 1997
• Grant date: Aug 31, 1999
• Expiry date: Nov 13, 2017

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F7/508
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A combined adder and logic unit having a reduced operation delay of arithmetic and logic operations, and providing an improved fan in and reduced wiring delays and capacity if implemented in the arithmetic and logic section of a microprocessor chip. The unit comprises a carry network (30) connected to operand inputs for generating carry-out signals of the byte positions (By0-By7) and further comprises a pre-sum logic (32) having a bit function generator (42) and a sum generator (45, 46, 48). Said bit function generator derives from the operands Ai and Bi bit functions Gi, Pi which are provided as logic function output and as input to said sum generator for producing preliminary arithmetic functions (SUM0, SUM1) to anticipate carry-in signals of one or zero. A result selector (70) is controlled by a byte position carry-out signal (Cy55) from the carry network means and by operation control signals to select from the output of said pre-sum logic one of the arithmetic functions (SUM0, SUM1) or one of the logic functions as result of the unit operation.