Method and apparatus for generating carries in an adder circuit
US5944777A · kind A · utility
3Cited by
7References
3Claims
0Family size
Assignee
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Key dates
| Filing date | May 5, 1997 |
| Grant date | Aug 31, 1999 |
| Priority date | — |
| Expiry date | May 5, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/508
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An adder circuit to generate carry-outs and a method implemented by the adder circuit. First and second groups of consecutive group generate terms are calculated. The first group of group generate terms are combined to calculate a first result at a first logic level, and the second group of group generate terms are combined to calculate a second result at the same logic level. The first and second results are then combined to calculate a carry-out at a second logic level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.