Direct memory access unit having a definable plurality of transfer channels
US5944800A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 12, 1997 |
| Grant date | Aug 31, 1999 |
| Priority date | — |
| Expiry date | Sep 12, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Th present invention relates to a DMA-controller having a definable plurality of transfer channels. According to the present invention such a unit comprises a data processing unit with a bus interface unit being coupled with a bus for transferring data. The data processing unit executes a data transfer on said bus dependent on programmable parameters. It further comprises a parameter memory storing those parameters for each transfer channel, whereby the parameter memory provides a first memory area which stores for each defined transfer channel a word comprising a vector address to a second memory area comprising specific parameters for said transfer channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.