System and method for transmitting data upon an address portion of a computer system bus during periods of maximum utilization of a data portion of the bus
US5944805A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 21, 1997 |
| Grant date | Aug 31, 1999 |
| Priority date | — |
| Expiry date | Aug 21, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4217
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method are presented for transmitting data upon an address portion of a computer system bus during periods of maximum or near-maximum utilization of a data portion of the bus. One embodiment of the computer system includes at least one central processing unit (CPU) and a main memory coupled to a processor bus. The main memory stores data, and the CPU executes instructions stored within the main memory. The processor bus is a split transaction bus. The processor bus is divided into an address bus, a data bus, and a control bus including address, data, and control signal lines, respectively. The CPU and the main memory each include a bus interface, and are coupled to the processor bus via the bus interface. The bus interface includes a transaction queue coupled to an interface unit. The interface unit is coupled to the address, data, and control buses, and performs bus transactions (i.e., read and/or write transactions) upon the processor bus. The split bus transactions are coordinated using tag values generated by the CPU. The transaction queue stores a list of pending data exchange operations. Each interface unit competes for control of the address and data buses. When…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.