Compact ISA-bus interface
US5944807A · kind A · utility
3Cited by
16References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 6, 1996 |
| Grant date | Aug 31, 1999 |
| Priority date | — |
| Expiry date | Feb 6, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4027
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An I/O interface, compatible with industry standards, for interfacing a host to a peripheral device. The interface includes a clock signal, a bus, an address latch enable signal, a peripheral device ready signal, a command signal, a device selected backoff signal, and a reset signal, resulting in an I/O interface capable of ISA-compatible operation with only 22 pins. Address, data, command, interrupt request, and DMA request information are communicated between the host and the peripheral device via a single bus by multiplexing the information on the bus using phasing techniques.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.