Controlling flash memory program and erase pulses
US5944837A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 18, 1997 |
| Grant date | Aug 31, 1999 |
| Priority date | — |
| Expiry date | Aug 18, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An operation control method and apparatus are described. The apparatus includes a timer circuit, a blocking circuit and a control circuit. The timer circuit provides a done signal upon completion of timing a predetermined elapsed time interval initiated by a start signal. The blocking circuit receives the done signal and provides the done signal as output if the done signal is not blocked when received. The control circuit receives a begin signal indicating that the operation is to be performed and a limit signal to indicate whether or not a condition exists that would prevent the operation from being completed in a single step. If the limit signal indicates the operation can be completed in the single step, the control circuit starts the timing circuit and controls performance of the single step until the done signal is received. If the limit signal indicates the operation cannot be completed in the single step, the control circuit divides the single step into at least two sub-steps, during each sub-step, the control circuit starts the timing circuit and controls performance of the sub-step until the done signal is received. The control circuit blocks output of the done signal fro…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.