Circuit and method to prevent inadvertent test mode entry
US5944845A · kind A · utility
14Cited by
8References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 26, 1997 |
| Grant date | Aug 31, 1999 |
| Priority date | — |
| Expiry date | Jun 26, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31701
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A test vector decode circuit includes a lockout circuit to prevent inadvertent latching of output vectors. This circuit is driven by an additional output vector from the circuit. The additional output vector, as well as the other output vectors, undergo at least one latching. The signal transmitted by the additional output vector as a result of the final latching activates the lockout circuit. The test vector decode circuit also receives a supervoltage signal. Only by turning off the supervoltage signal can all of the output test vectors be reset, including the additional output vector.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.