Memory device
US5945706A · kind A · utility
36Cited by
4References
17Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 25, 1998 |
| Grant date | Aug 31, 1999 |
| Priority date | — |
| Expiry date | Feb 25, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device and method of forming the same, includes a plurality of wordlines for applying a cell driving signal, a plurality of bitlines for inputting or outputting data, and a plurality of cells, each cell having a first gate, source and drain electrodes and a second gate, wherein either the first or second gate is connected to one of the wordlines, the source electrode is connected to one of the bitlines, and the drain electrode is connected to either the first or second gate which is not connected to the one wordline.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.