Self-aligned metal-oxide-compound semiconductor device and method of fabrication
US5945718A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 12, 1998 |
| Grant date | Aug 31, 1999 |
| Priority date | — |
| Expiry date | Feb 12, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/85
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A self-aligned enhancement mode metal-oxide-compound semiconductor FET (10) includes a stoichiometric Ga.sub.2 O.sub.3 gate oxide layer (14) positioned on upper surface (16) of a compound semiconductor wafer structure (13). The stoichiometric Ga.sub.2 O.sub.3 layer forms an atomically abrupt interface with the compound semiconductor wafer structure. A refractory metal gate electrode (17) is positioned on upper surface (18) of the stoichiometric Ga.sub.2 O.sub.3 gate oxide layer (14). The refractory metal is stable on the stoichiometric Ga.sub.2 O.sub.3 gate oxide layer at elevated temperature. Self-aligned source and drain areas, and source and drain contacts (19, 20) are positioned on the source and drain areas (21, 22).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.