High-speed bus structure for printed circuit boards
US5945886A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 19, 1997 |
| Grant date | Aug 31, 1999 |
| Priority date | — |
| Expiry date | Sep 19, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10689
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides for high speed signal buses in printed circuit boards. For high speed operation, each signal line of a bus has substantially the same electrical length as the other signal lines and forms a loop in two halves, each half electrically shielded from the other half. Each signal line has a first and a second terminal, with each terminal connected to a reference bias voltage through a first resistance which matches a loaded characteristic impedance of the signal line. The reference bias voltage is set at a midpoint of signal voltage swings on the signal line. Such high speed buses have particular applications to high speed memory systems with DRAMs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.