Secondary ESD/EOS protection circuit
US5946175A · kind A · utility
48Cited by
3References
16Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 17, 1998 |
| Grant date | Aug 31, 1999 |
| Priority date | — |
| Expiry date | Feb 17, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/08122
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
To protect an input buffer from gate-oxide breakdown failure during an ESD/EOS event, an inventive secondary protection circuit is disclosed. In one embodiment, the protection circuit includes a first switch terminal connected to a pad, a second switch terminal connected to the buffer of an internal circuit, a control terminal, and an RC circuit connected between the control terminal and the supply voltage Vcc. The RC circuit delays a propagation of an ESD/EOS voltage from Vcc to the control terminal, so as to delay a generation of a conductive path between the first and second switch terminals until the ESD/EOS event lapses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.