Computer implemented method for estimating fabrication yield for semiconductor integrated circuit including memory blocks with redundant rows and/or columns
US5946214A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 11, 1997 |
| Grant date | Aug 31, 1999 |
| Priority date | — |
| Expiry date | Jul 11, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B99/22
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A computer is used to estimate a fabrication yield for a semiconductor product under design which includes a plurality of integrated circuit dies, each of which includes a memory cache having a predetermined redundancy scheme in the form of redundant rows and/or columns. A bitmap failure analysis of an existing semiconductor product including a plurality of integrated circuit dies having bitmap failure modes that are comparable to those of the product being designed is performed to obtain a number of failed caches. An observed repair rate is computed as a ratio of a number of the failed caches that can be repaired by the predetermined redundancy scheme to the number of failed caches. A model repair rate for the predetermined redundancy scheme which approximates the observed repair rate is computed using a multiple Poisson model including computed average numbers .lambda. of failures for the failure modes respectively. The numbers .lambda. are optimized by minimizing a least squares difference between the observed repair rates and the model repair rates. The fabrication yield is computed as a predetermined function of the model repair rate including scale factor(s) for the circuit o…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.