SRAM device having negative voltage generator for performing stable data latch operation
US5946225A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 8, 1998 |
| Grant date | Aug 31, 1999 |
| Priority date | — |
| Expiry date | May 8, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4125
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A SRAM device according to the present invention performs a stable data latch operation. The present invention provides a negative voltage generator which is coupled to the drive transistors in the SRAM device for providing negative voltage for the drive transistors during a read cycle of the SRAM device when a word line of the SRAM device is activated. The negative voltage generator includes an output terminal coupled to access transistors, a current path for discharging the output terminal up to a ground voltage level in response to control signals, and a pump for pumping the output terminal to make the output terminal be in a negative voltage level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.