Semiconductor stack structures and fabrication/sparing methods utilizing programmable spare circuit
US5946545A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 2, 1997 |
| Grant date | Aug 31, 1999 |
| Priority date | — |
| Expiry date | Oct 2, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Electronic semiconductor structures, and fabrication and sparing methods, each utilize an electrically programmable spare circuit incorporated with a multichip package. The programmable sparing capability in the multichip package is accomplished either with or without the inclusion of a spare chip(s). With a spare memory circuit, individual failed memory cells in the semiconductor chips of a stack can be functionally replaced by memory cells of the spare memory circuit subsequent to encapsulation and burn-in testing. With use of a spare chip, non-volatile sparing can occur subsequent to encapsulation and burn-in testing without physical rewiring of a wire bond connection. Specific details of alternate electronic semiconductor structures, and fabrication and sparing methods therefore, are set forth.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.