ESD protection for high density DRAMs using triple-well technology
US5949094A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 29, 1997 |
| Grant date | Sep 7, 1999 |
| Priority date | — |
| Expiry date | Aug 29, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/713
Abstract
An ESD protected semiconductor circuit and the ESD protection circuit. The protected circuit includes a terminal, a semiconductor device coupled to the terminal and an ESD protection circuit. The ESD protection circuit includes a substrate of a first conductivity type and has a surface. A first well of conductivity type opposite to the first conductivity type is disposed within the substrate and extends to the surface. A second well of the first conductivity type is disposed within the first well and is spaced from the substrate and extending to the surface. A third region of the opposite conductivity type is disposed within the second well and is spaced from the first well and extending to the surface. At least one of the substrate or the third region is coupled to the terminal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.