E. Ajith Amerasekera
13Patents
9h-index
20Co-inventors
64Inventor score
Filing activity: Jul 1, 1996 → Jul 9, 2002
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6081002A | Lateral SCR structure for ESD protection in trench isolated technologies | Electricity | 63 | Expired |
| US6040968A | EOS/ESD protection for high density integrated circuits | Electricity | 40 | Expired |
| US5930094A | Cascoded-MOS ESD protection circuits for mixed voltage chips | Electricity | 29 | Expired |
| US6143594A | On-chip ESD protection in dual voltage CMOS | Electricity | 26 | Expired |
| US6137144A | On-chip ESD protection in dual voltage CMOS | Electricity | 16 | Expired |
| US5949094A | ESD protection for high density DRAMs using triple-well technology | Electricity | 14 | Expired |
| US6628493B1 | System and method for electrostatic discharge protection using lateral PNP or PMOS or both for substrate biasing | Electricity | 13 | Expired |
| US6530064B1 | Method and apparatus for predicting an operational lifetime of a transistor | Physics | 11 | Expired |
| US6469353B1 | Integrated ESD protection circuit using a substrate triggered lateral NPN | Electricity | 9 | Expired |
| US5804860A | Integrated lateral structure for ESD protection in CMOS/BiCMOS technologies | Emerging Cross-Sectional Technologies | 6 | Expired |
| US6433392B1 | Electrostatic discharge device and method | Electricity | 6 | Expired |
| US5793083A | Method for designing shallow junction, salicided NMOS transistors with decreased electrostatic discharge sensitivity | Electricity | 2 | Expired |
| US7456477B2 | Electrostatic discharge device and method | Electricity | 1 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.