Soft latch circuit having sharp-cornered hysteresis characteristics
US5949265A · kind A · utility
6Cited by
7References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 31, 1997 |
| Grant date | Sep 7, 1999 |
| Priority date | — |
| Expiry date | Oct 31, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/013
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A soft latch circuit having a first and second inverter is disclosed. The output of the first inverter is connected to the input of the second inverter, and the output of the second inverter is connected to the input of the first inverter. The first inverter includes a complimentary pair of field-effect transistors (FETs). The second inverter includes either a complimentary pair of current mirrors, or a current mirror and a complimentary FET, the latter providing improved noise immunity characteristics when the soft latch is set in only one direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.