John A. Bracchitta
25Patents
13h-index
33Co-inventors
77Inventor score
Filing activity: May 5, 1995 → Feb 16, 2007
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6483156B1 | Double planar gated SOI MOSFET structure | Electricity | 139 | Expired |
| US6677637B2 | Intralevel decoupling capacitor, method of manufacture and testing circuit of the same | Emerging Cross-Sectional Technologies | 46 | Expired |
| US6130469A | Electrically alterable antifuse using FET | Electricity | 41 | Expired |
| US6100123A | Pillar CMOS structure | Electricity | 36 | Expired |
| US6882015B2 | Intralevel decoupling capacitor, method of manufacture and testing circuit of the same | Emerging Cross-Sectional Technologies | 30 | Expired |
| US6660596B2 | Double planar gated SOI MOSFET structure | Electricity | 28 | Expired |
| US6373095B1 | NVRAM cell having increased coupling ratio between a control gate and floating gate without an increase in cell area | Electricity | 27 | Expired |
| US5518945A | Method of making a diffused lightly doped drain device with built in etch stop | Emerging Cross-Sectional Technologies | 26 | Expired |
| US6261895A | Polysilicon capacitor having large capacitance and low resistance and process for forming the capacitor | Electricity | 21 | Expired |
| US6060358A | Damascene NVRAM cell and method of manufacture | Electricity | 21 | Expired |
| US5734192A | Trench isolation for active areas and first level conductors | Electricity | 17 | Expired |
| US7195971B2 | Method of manufacturing an intralevel decoupling capacitor | Emerging Cross-Sectional Technologies | 16 | Expired |
| US6020777A | Electrically programmable anti-fuse circuit | Physics | 16 | Expired |
| US7089192B2 | Intellectual property management method and apparatus | Emerging Cross-Sectional Technologies | 13 | Expired |
| US6394638B1 | Trench isolation for active areas and first level conductors | Electricity | 8 | Expired |
| US5949265A | Soft latch circuit having sharp-cornered hysteresis characteristics | Electricity | 6 | Expired |
| US6339015B1 | Method of fabricating a non-volatile semiconductor device | Electricity | 5 | Expired |
| US6255699A | Pillar CMOS structure | Electricity | 4 | Expired |
| US6232633A | NVRAM cell using sharp tip for tunnel erase | Electricity | 2 | Expired |
| US6420746B1 | Three device DRAM cell with integrated capacitor and local interconnect | Electricity | 0 | Expired |
| US7323382B2 | Intralevel decoupling capacitor, method of manufacture and testing circuit of the same | Emerging Cross-Sectional Technologies | 0 | Active |
| US6063687A | Formation of trench isolation for active areas and first level conductors | Electricity | 0 | Expired |
| US6858889B2 | Polysilicon capacitor having large capacitance and low resistance | Electricity | 0 | Expired |
| US6344381B1 | Method for forming pillar CMOS | Electricity | 0 | Expired |
| US7630915B2 | Intellectual property management method and apparatus | Emerging Cross-Sectional Technologies | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.