Method for aligning shallow trench isolation
US5950093A · kind A · utility
Inventor
Key dates
| Filing date | Dec 30, 1998 |
| Grant date | Sep 7, 1999 |
| Priority date | — |
| Expiry date | Dec 30, 2018 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/975
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for aliging a shallow trench isolation is provided. An aligning mark which is deeper than a prior technique is formed in a provided substrate. A trench is formed and an aligning trench is formed in the position over the aligning mark. A thick oxide layer is deposited on the semiconiductol substrate, in the trench and in the aligning trench. After a portion of the thick oxide layer removed, another portion of the thick oxide layer is removed by etching back. A gate oxide layer is formed on a substrate comprising the trench and the aligning trench. A polysilicon layer with the step-height profile in the position over the aligning mark is formed on the gate oxide layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.