Methods for reducing etch rate loading while etching through a titanium nitride anti-reflective layer and an aluminum-based metallization layer
US5952244A · kind A · utility
11Cited by
23References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 15, 1996 |
| Grant date | Sep 14, 1999 |
| Priority date | — |
| Expiry date | Feb 15, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32136
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method, in a plasma processing chamber, for etching through a selected portion of layers of a wafer stack, which comprises an anti-reflective layer and a metallization layer disposed below the anti-reflective layer. The method comprises the step of etching at least partially through the anti-reflective layer of the wafer stack with a first chemistry that comprises both an etchant chemical and a polymer-forming chemical. Further, the method comprises the step of etching at least partially through the metallization layer of the wafer stack with a second chemistry different from the first chemistry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.