CMOS output buffer protection circuit
US5952866A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 28, 1998 |
| Grant date | Sep 14, 1999 |
| Priority date | — |
| Expiry date | Apr 28, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0018
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A low voltage CMOS output buffer protection circuit is configured to protect an associated output buffer from any high voltage signals (e.g., 5V) that may appear along a signal bus line. The protection circuit is also "hot-pluggable", meaning that the protection circuit will not draw any current when not powered (i.e., when VDD is not present). An on-chip reference voltage generator is used to provide a reference voltage VDD2 that will be essentially equal to VDD as long as VDD is present. When VDD is not present, VDD2 will track the signal appearing along the signal bus (PAD), remaining at least two diode drops below the PAD voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.