Integrated circuit memory devices having cross-coupled isolation gate controllers which provide simultaneous reading and writing capability to multiple memory arrays
US5953259A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 24, 1998 |
| Grant date | Sep 14, 1999 |
| Priority date | — |
| Expiry date | Jun 24, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Preferred integrated circuit memory devices have the capability of connecting a sense amplifier to multiple arrays of memory one-at-a-time or simultaneously, in response to first and second control signals, respectively. These memory devices include first and second memory arrays which have first and second pairs of differential input/output lines electrically coupled thereto, respectively. A sense amplifier is also provided having first and second pairs of differential input/output lines. To provide independent or simultaneous access to the first and second memory arrays by the sense amplifier, preferred isolation and equalization circuits are provided. With these circuits, a first electrical connection can be formed between the first pairs of differential input/output lines of the first memory array and the sense amplifier and a second electrical connection can be simultaneously formed between the second pairs of differential input/outlput lines of the second memory array and the sense amplifier, when a control signal line is in a first logic state (e.g., logic 0). These preferred isolation and equalization circuits also preclude simultaneous formation of the first and second ele…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.