Customization of integrated circuits
US5953577A · kind A · utility
8Cited by
12References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 29, 1998 |
| Grant date | Sep 14, 1999 |
| Priority date | — |
| Expiry date | Sep 29, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/525
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for patterning a layer of photoresist includes the steps of 1) exposing the photoresist through a standard precision mask to define all possible cut points, 2) etching all possible cut points in a dielectric layer, 3) selectively exposing a second layer of photoresist with a non-precision targeting energy beam or mask to select the desired cut points. Consequently, no custom precision masks are required to pattern the various layers of photoresist during the fabrication of application specific integrated circuits (ASICs), thereby reducing both the lead-time and costs for manufacturing ASICS.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.