CLEARLOGIC
🏢 View company profile →25Patents
1Active
25Granted
33Portfolio score
Filing activity: Mar 19, 1997 → May 21, 2020
Most-cited patents
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5885749A | Method of customizing integrated circuits by selective secondary deposition of layer interconnect material | Electricity | 255 | Expired |
| US6311316A | Designing integrated circuit gate arrays using programmable logic device bitstreams | Physics | 55 | Expired |
| US6348742B1 | Sacrificial bond pads for laser configured integrated circuits | Electricity | 23 | Expired |
| US5949323A | Non-uniform width configurable fuse structure | Electricity | 21 | Expired |
| US5840627A | Method of customizing integrated circuits using standard masks and targeting energy beams for single resist development | Emerging Cross-Sectional Technologies | 20 | Expired |
| US5986319A | Laser fuse and antifuse structures formed over the active circuitry of an integrated circuit | Electricity | 20 | Expired |
| US6225652A | Vertical laser fuse structure allowing increased packing density | Electricity | 18 | Expired |
| US6078091A | Inter-conductive layer fuse for integrated circuits | Electricity | 17 | Expired |
| US6060330A | Method of customizing integrated circuits by selective secondary deposition of interconnect material | Electricity | 11 | Expired |
| US5985518A | Method of customizing integrated circuits using standard masks and targeting energy beams | Electricity | 9 | Expired |
| US6191641A | Zero power fuse circuit using subthreshold conduction | Physics | 9 | Expired |
| US5953577A | Customization of integrated circuits | Electricity | 8 | Expired |
| USD963156S1 | Face mask | General | 8 | Active |
| US5945238A | Method of making a reusable photolithography mask | Physics | 8 | Expired |
| US6096566A | Inter-conductive layer fuse for integrated circuits | Electricity | 8 | Expired |
| US6080533A | Method of patterning photoresist using precision and non-precision techniques | Emerging Cross-Sectional Technologies | 8 | Expired |
| US6020648A | Die structure using microspheres as a stress buffer for integrated circuit prototypes | Electricity | 7 | Expired |
| US5989783A | Method of customizing integrated circuits by depositing two resist layers to selectively pattern layer interconnect material | Emerging Cross-Sectional Technologies | 7 | Expired |
| US6228564A | Method of patterning photoresist using precision and non-precision techniques | Emerging Cross-Sectional Technologies | 5 | Expired |
| US6369437B1 | Vertical fuse structure for integrated circuits and a method of disconnecting the same | Electricity | 5 | Expired |
| US6346748B1 | Electronic circuit structure with photoresist layer that has non-precision openings formed by a laser | Electricity | 5 | Expired |
| US6239480A | Modified lead frame for improved parallelism of a die to package | Electricity | 3 | Expired |
| US6235556A | Method of improving parallelism of a die to package using a modified lead frame | Electricity | 3 | Expired |
| US6087200A | Using microspheres as a stress buffer for integrated circuit prototypes | Electricity | 1 | Expired |
| US6531756B1 | Laser fuse and antifuse structures formed over the active circuitry of an integrated circuit | Electricity | 0 | Expired |
Source: USPTO / EPO open patent data. Counts and citation impact are objective bibliographic measures.